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Precision Single and Dual Low Noise Operational Amplifiers
ISL28127, ISL28227
The ISL28127 and ISL28227 are very high precision amplifiers featuring very low noise, low offset voltage, low input bias current and low temperature drift making them the ideal choice for applications requiring both high DC accuracy and AC performance. The combination of precision, low noise, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls, and industrial controls. The ISL28127 single and ISL28227 dual are available in an 8 Ld SOIC, TDFN and MSOP packages. All devices are offered in standard pin configurations and operate over the extended temperature range to -40C to +125C.
Features
* Very Low Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . .2.5nV/Hz * Low Input Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70V, Max. * Superb Offset Drift. . . . . . . . . . . . . . . . . . . . . . 0.5V/C, Max. * Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA, Max. * Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V * Gain-bandwidth Product . . . . . . . . . 10MHz Unity Gain Stable * No Phase Reversal
Applications
* Precision Instruments * Medical Instrumentation * Industrial Controls * Active Filter Blocks * Data Acquisition * Power Supply Control
Related Literature
* AN1508: ISL281x7SOICEVAL1Z Evaluation Board User's Guide * AN1509: ISL282x7SOICEVAL1Z Evaluation Board User's Guide
INPUT NOISE VOLTAGE (nV/Hz)
C1
1.5nF
100 VS = 19V AV = 1
V+
VIN R1
95.3
R2
OUTPUT
10
+
232 68.3nF
C2
V-
Sallen-Key Low Pass Filter (1MHz)
1 0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL DENSITY
December 16, 2010 FN6633.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL28127, ISL28227 Ordering Information
.
PART NUMBER (Notes 1, 2, 3) ISL28127FBZ ISL28127FRTBZ ISL28127FRTZ ISL28127FUBZ ISL28127FUZ ISL28227FBZ ISL28227FRTBZ ISL28227FRTZ ISL28227FUBZ ISL28227FUZ ISL28127SOICEVAL1Z ISL28127MSOPEVAL1Z ISL28227SOICEVAL2Z
PART MARKING 28127 FBZ 8127 -C 8127 8127Z 8127Z -C 28227 FBZ 8227 -C 8227 8227Z 8227Z -C Evaluation Board Evaluation Board Evaluation Board
VOS (MAX) (V) 70 75 (B Grade) 150 (C Grade) 70 (B Grade) 150 (C Grade) 75 75 (B Grade) 150 (C Grade) 75 (B Grade) 150 (C Grade) 8 Ld SOIC
PACKAGE (Pb-Free) M8.15E L8.3x3A L8.3x3A M8.118 M8.118 M8.15E L8.3x3A L8.3x3A M8.118 M8.118
PKG. DWG. #
8 Ld TDFN 8 Ld TDFN 8 Ld MSOP 8 Ld MSOP 8 Ld SOIC 8 Ld TDFN 8 Ld TDFN 8 Ld MSOP 8 Ld MSOP
1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28127, ISL28227. For more information on MSL please see techbrief TB363.
2
FN6633.6 December 16, 2010
ISL28127, ISL28227 Pin Configurations
ISL28127 (8 LD SOIC, MSOP) TOP VIEW
NC -IN_A +IN_A V1 2 3 4 -+ 8 7 6 5 NC V+ VOUTA NC VOUTA -IN_A +IN_A V-
ISL28227 (8 LD SOIC, MSOP) TOP VIEW
1 2 3 4 -+ +8 7 6 5 V+ VOUTB -IN_B +IN_B
ISL28127 (8 LD TDFN) TOP VIEW
NC 1 -IN 2 +IN 3 V- 4 PD -+ 8 NC 7 V+ 6 VOUT 5 NC VOUTA 1 -IN_A 2 +IN_A 3 V- 4
ISL28227 (8 LD TDFN) TOP VIEW
8 V+ -+ PD +7 VOUTB 6 -IN_B 5 +IN_B
Pin Descriptions
ISL28127 (8 LD SOIC, 8 LD MSOP) ISL28127 (8 LD TDFN) 3 3 4 4 3 4 5 2 6 6 7 7 6 2 1, 5, 8 1, 5, 8 PD 7 8 1 2 7 8 1 2 6 3 4 5 ISL28227 (8 LD SOIC, 8 LD MSOP) ISL28227 (8 LD TDFN) PIN NAME +IN +IN_A V+IN_B -IN -IN_B VOUT VOUTB V+ VOUTA -IN_A NC PD EQUIVALENT CIRCUIT Circuit 1 Circuit 1 Circuit 3 Circuit 1 Circuit 1 Circuit 1 Circuit 2 Circuit 2 Circuit 3 Circuit 2 Circuit 1 DESCRIPTION Amplifier non-inverting input Amplifier A non-inverting input Negative power supply Amplifier B non-inverting input Amplifier inverting input Amplifier B inverting input Amplifier output Amplifier B output Positive power supply Amplifier A output Amplifier A inverting input Not Connected - This pin is not electrically connected internally. Thermal Pad. Pad should be connected to lowest potential source in the circuit.
V+ CAPACITIVELY TRI GGERED ESD CLAMP VCIRCUIT 3
V+ ININ+
V+ OUT V-
V-
CIRCUIT 1
CIRCUIT 2
3
FN6633.6 December 16, 2010
ISL28127, ISL28227
Absolute Maximum Ratings
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 8 Ld SOIC (Note 5, 7) ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . . 120 60 ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . . 110 55 8 Ld TDFN (Notes 4, 6) ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . . 48 7 ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . . 47 6 8 Ld MSOP (Note 5, 7) ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . . 155 50 ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . . 150 45 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40C to +125C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 7. For JC, the "case temp" location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VOS
VS 15V, VCM = 0, VO = 0V, RL = Open, TA= +25C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +125C.
MIN CONDITIONS ISL28127
DESCRIPTION Offset Voltage; SOIC Package
(Note 8)
-70 -120
TYP 10 10 -10 -10 -10 -10 -
MAX (Note 8) 70 120 75 150 70 150 75 160 75 150 150 250
UNIT V V V V V V V V V V V V
ISL28227
-75 -150
Offset Voltage; MSOP Grade B Package Offset Voltage; TDFN Grade B Package Offset Voltage; MSOP, TDFN Grade B Package Offset Voltage; MSOP, TDFN Grade C Package
ISL28127
-70 -150
ISL28127
-75 -160
ISL28227
-75 -150
ISL28127 ISL28227
-150 -250
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FN6633.6 December 16, 2010
ISL28127, ISL28227
Electrical Specifications
PARAMETER TCVOS
VS 15V, VCM = 0, VO = 0V, RL = Open, TA= +25C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued)
MIN CONDITIONS ISL28127 ISL28227 ISL28127 ISL28127 ISL28227 ISL28127 ISL28227
DESCRIPTION Offset Voltage Drift; SOIC Package Offset Voltage Drift; MSOP, Grade B Offset Voltage Drift; TDFN, Grade B Offset Voltage Drift; MSOP, TDFN, Grade B Offset Voltage Drift; MSOP, TDFN, Grade C
(Note 8)
-0.5 -0.75 -0.80 -0.90 -0.75 -1 -10 -12
TYP 0.1 0.1 0.1 0.1 0.1 0.1 1 1 120 125 117 1500 13.65 13.5 -13.65 -13.5 2.2 45 -
MAX (Note 8) 0.5 0.75 0.80 0.90 0.75 1 10 12 10 12 13 12 -13.5 -13.2 -13.4 -13.1 2.8 3.7 20
UNIT V/C V/C V/C V/C V/C V/C nA nA nA nA V V dB dB dB dB dB dB V/mV V V V V V V V V mA mA mA V
IOS
Input Offset Current
IB
Input Bias Current
-10 -12
VCM
Input Voltage Range
Guaranteed by CMRR
-13 -12
CMRR
Common-Mode Rejection Ratio
VCM = -13V to +13V VCM = -12V to +12V
115 115 115 115 110 110 1000 13.5 13.2
PSRR
Power Supply Rejection Ratio ISL28127 Power Supply Rejection Ratio ISL28227
VS = 2.25V to 20V VS = 3V to 20V VS = 2.25V to 20V VS = 3V to 20V VO = -13V to +13V RL = 10k to ground RL = 10k to ground
AVOL VOH
Open-Loop Gain Output Voltage High
RL = 2k to ground
13.4 13.1
VOL
Output Voltage Low
RL = 10k to ground
-
RL = 2k to ground
-
IS
Supply Current/Amplifier
-
ISC VSUPPLY GBW enp-p en en
Short-Circuit Supply Voltage Range
RL = 0 to ground Guaranteed by PSRR
2.25
AC SPECIFICATIONS
Gain Bandwidth Product Voltage Noise Voltage Noise Density Voltage Noise Density 0.1Hz to 10Hz f = 10Hz f = 100Hz 10 85 3 2.8 MHz nVP-P nV/Hz nV/Hz
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FN6633.6 December 16, 2010
ISL28127, ISL28227
Electrical Specifications
PARAMETER en en in THD + N
VS 15V, VCM = 0, VO = 0V, RL = Open, TA= +25C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued)
MIN CONDITIONS f = 1kHz f = 10kHz f = 10kHz 1kHz, G = 1, VO = 3.5VRMS, RL = 2k AV = 10, RL = 2k, VO = 4VP-P AV = -1, VOUT = 100mVP-P, Rf = Rg = 2k, RL = 2k to VCM AV = -1, VOUT = 100mVP-P, Rf = Rg = 2k, RL = 2k to VCM AV = -1 VOUT = 10VP-P, Rg = Rf =10k, RL = 2k to VCM AV = -1, VOUT = 10VP-P, RL = 2k to VCM AV = 100, VIN = 0.2V RL = 2k to VCM
DESCRIPTION Voltage Noise Density Voltage Noise Density Current Noise Density Total Harmonic Distortion + Noise
(Note 8)
-
TYP 2.5 2.5 0.4 0.00022
MAX (Note 8) -
UNIT nV/Hz nV/Hz pA/Hz %
TRANSIENT RESPONSE
SR tr, tf, Small Signal Slew Rate Rise Time 10% to 90% of VOUT Fall Time 90% to 10% of VOUT ts Settling Time to 0.1% 10V Step; 10% to VOUT Settling Time to 0.01% 10V Step; 10% to VOUT tOL Output Overload Recovery Time 3.6 36 38 3.4 3.8 1.7 V/s ns ns s s s
Electrical Specifications
PARAMETER VOS
VS 5V, VCM = 0, VO = 0V, TA = +25C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +125C.
MIN CONDITIONS ISL28127
DESCRIPTION Offset Voltage; SOIC Package
(Note 8)
-70 -120
TYP 10 10 -10 -10 -10 -10 0.1 0.1 0.1 0.1 0.1 0.1
MAX (Note 8) 70 120 75 150 70 150 75 160 75 150 150 250 0.5 0.75 0.80 0.90 0.75 1
UNIT V V V V V V V V V V V V V/C V/C V/C V/C V/C V/C
ISL28227
-75 -150
Offset Voltage; MSOP Grade B Package Offset Voltage; TDFN Grade B Package Offset Voltage; MSOP, TDFN Grade B Package Offset Voltage; MSOP, TDFN Grade C Package TCVOS Offset Voltage Drift; SOIC Package Offset Voltage Drift; MSOP, Grade B Offset Voltage Drift; TDFN, Grade B Offset Voltage Drift; MSOP, TDFN, Grade B Offset Voltage Drift; MSOP, TDFN, Grade C
ISL28127 ISL28127 ISL28227 ISL28127 ISL28227 ISL28127 ISL28227 ISL28127 ISL28127 ISL28227 ISL28127 ISL28227
-70 -150 -75 -160 -75 -150 -150 -250 -0.5 -0.75 -0.80 -0.90 -0.75 -1
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FN6633.6 December 16, 2010
ISL28127, ISL28227
Electrical Specifications
PARAMETER IOS
VS 5V, VCM = 0, VO = 0V, TA = +25C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +125C.
MIN CONDITIONS
DESCRIPTION Input Offset Current
(Note 8)
-10 -12
TYP 1 1 120 125 1500 3.65 3.5 -3.65 -3.5 2.2 45
MAX (Note 8) 10 12 10 12 3 2 -3.5 -3.2 -3.4 -3.1 2.8 3.7 -
UNIT nA nA nA nA V V dB dB dB dB V/mV V V
IB
Input Bias Current
10 -12
VCM
Common Mode Input Voltage Range
Guaranteed by CMRR
-3 -2
CMRR
Common-Mode Rejection Ratio
VCM = -3V to +3V VCM = -2V to +2V VS = 2.25V to 5V VS = 3V to 5V VO = -3V to +3V RL = 10k to ground RL = 10k to ground
115 115 115 115 1000 3.5 3.2
PSRR
Power Supply Rejection Ratio
AVOL VOH
Open-Loop Gain Output Voltage High
RL = 2k to ground
3.4 3.1
V V V
VOL
Output Voltage Low
RL = 10k to ground
-
RL = 2k to ground
-
V mA mA mA
IS
Supply Current/Amplifier
-
ISC GBW THD + N
Short-Circuit
-
AC SPECIFICATIONS
Gain Bandwidth Product Total Harmonic Distortion + Noise 1kHz, G = 1, Vo = 2.5VRMS, RL = 2k AV = 10, RL = 2kOH AV = -1, VOUT = 100mVP-P, Rf = Rg = 2k, RL = 2k to VCM AV = -1, VOUT = 100mVP-P, Rf = Rg = 2k, RL = 2k to VCM AV = -1, VOUT = 4VP-P, Rf = Rg = 2k, RL = 2k to VCM AV = -1, VOUT = 4VP-P, Rf = Rg = 2k, RL = 2k to VCM 10 0.0034 MHz %
TRANSIENT RESPONSE
SR tr, tf, Small Signal Slew Rate Rise Time 10% to 90% of VOUT Fall Time 90% to 10% of VOUT ts Settling Time to 0.1% Settling Time to 0.01% 3.6 36 38 1.6 4.2 V/s ns ns s s
NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7
FN6633.6 December 16, 2010
ISL28127, ISL28227 Typical Performance Curves VS = 15V, VCM = 0V, RL = Open, unless otherwise specified.
100 80 60 40 20 0 -20 -40 -60 -80 0 1 2 3 4 5 V+ = 38V RL = 10k CL = 3.5pF Rg = 10, Rf = 100k AV = 10,000 6 7 8 9 10 TIME (s)
INPUT NOISE VOLTAGE (nV/Hz)
INPUT NOISE VOLTAGE (nV)
100 VS = 19V AV = 1
10
-100
1 0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 3. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
FIGURE 4. INPUT NOISE VOLTAGE SPECTRAL DENSITY
INPUT NOISE CURRENT (pA/Hz)
100 VS = 19V AV = 1
PSRR (dB )
10
1
0.1 0.1
130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10
PSRR+ and PSRR- VS = 5V RL = INF CL = 5.25pF AV = +1 VS = 1VP-P PSRR+ and PSRR- VS = 15V
1
10
100
1k
10k
100k
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. INPUT NOISE CURRENT SPECTRAL DENSITY
FIGURE 6. PSRR vs FREQUENCY, VS = 5V, 15V
130 VS = 5V 120 110 VS = 2.25V 100 90 80 70 VS = 15V 60 50 40 RL = INF 30 CL = 5.25pF 20 AV = +1 10 0 VCM = 1VP-P -10 10 100 1k 10k 100k FREQUENCY (Hz)
100
50 VOS (V) VS = 5 0 VS = 15 -50
CMRR (dB )
1M
10M
-100 -50
0
50 100 TEMPERATURE (C)
150
FIGURE 7. CMRR vs FREQUENCY, VS = 2.25, 5V, 15V
FIGURE 8. VOS vs TEMPERATURE vs VSUPPLY
8
FN6633.6 December 16, 2010
ISL28127, ISL28227 Typical Performance Curves VS = 15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
5000 4000 3000 2000 IB+ (pA) IB- (pA) 1000 0 VS = 15 5000 4000 3000 2000 1000 0 -1000 -2000 VS = 5 -3000 -4000 0 50 100 TEMPERATURE (C) 150 -5000 -50 -25 0 25 50 75 100 125 150 VS = 5 VS = 15
-1000 -2000 -3000 -4000 -5000 -50
TEMPERATURE (C)
FIGURE 9. IB+ vs TEMPERATURE vs SUPPLY VOLTAGE
FIGURE 10. IB- vs TEMPERATURE vs SUPPLY VOLTAGE
5000 4000 3000 2000 IOS (pA) 1000 0 -1000 -2000 -3000 -4000 -5000 -50 -25 0 25 50 75 100 125 150 VS = 15 VS = 5 VOS (V)
60 29 UNITS 40 20 0 -20 -40 -60 -15 -10 -5 0 -40C AVERAGE
+25C +125C
5
10
15
TEMPERATURE (C)
INPUT COMMON MODE VOLTAGE
FIGURE 11. IOS vs TEMPERATURE vs SUPPLY VOLTAGE
FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = 15V
600 NUMBER OF AMPLIFIERS 500 400 300 200 100 0 -70
VS = 15V NUMBER OF AMPLIFIERS
600 500 400 300 200 100 0 -70
VS = 5V
-55
-40
-25
-10
5
20
35
50
65
-55
-40
-25
-10
5
20
35
50
65
VOS (V)
VOS (V)
FIGURE 13. INPUT OFFSET VOLTAGE DISTRIBUTION, VS = 15V
FIGURE 14. INPUT OFFSET VOLTAGE DISTRIBUTION, VS = 5V
9
FN6633.6 December 16, 2010
ISL28127, ISL28227 Typical Performance Curves VS = 15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
30 Vs = 15V NUMBER OF AMPLIFIERS 25 20 15 10 5 0 -0.7 NUMBER OF AMPLIFIERS 25 20 15 10 5 0 30 Vs = 5V
-0.5
-0.3
-0.1 0.1 0.3 VOS TC (V/C)
0.5
0.7
-0.7
-0.5
-0.3 -0.1 0.1 VOS TC (V/C)
0.3
0.5
0.7
FIGURE 15. OFFSET VOLTAGE DRIFT DISTRIBUTION, VS = 15V
FIGURE 16. OFFSET VOLTAGE DRIFT DISTRIBUTION, VS = 5V
40 NUMBER OF AMPLIFIERS 35 30 25 20 15 10 5 0 -22.5 -15 -7.5 0 7.5 IB+ TC (pA/C)
Vs = 15V NUMBER OF AMPLIFIERS
35 30 25 20 15 10 5 0 -25 -20 -15 -10 -5 0 10 5 IB+ TC (pA/C)
Vs = 5V
15
22.5
15
20
25
FIGURE 17. IB+ INPUT BIAS CURRENT DRIFT DISTRIBUTION, VS = 15V
FIGURE 18. IB+ INPUT BIAS CURRENT DRIFT DISTRIBUTION, VS = 5V
45 NUMBER OF AMPLIFIERS 40 35 30 25 20 15 10 5 0 -27 -18 -9 0 9 IB- TC (pA/C)
Vs = 15V NUMBER OF AMPLIFIERS
35 30 25 20 15 10 5 0 -30 -24 -18 -12 -6 6 12 0 IB- TC (pA/C)
Vs = 5V
18
27
18
24
30
FIGURE 19. IB- INPUT BIAS CURRENT DRIFT DISTRIBUTION, VS = 15V
FIGURE 20. IB- INPUT BIAS CURRENT DRIFT DISTRIBUTION, VS = 5V
10
FN6633.6 December 16, 2010
ISL28127, ISL28227 Typical Performance Curves VS = 15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
70 NUMBER OF AMPLIFIERS 60 50 40 30 20 10 0 -27 -18 -9 0 9 IOS TC (pA/C) 18 27 VS = 15V NUMBER OF AMPLIFIERS 50 45 40 35 30 25 20 15 10 5 0 12 -30 -24 -18 -12 -6 0 6 IOS TC (pA/C) 18 24 30 VS = 5V
FIGURE 21. INPUT OFFSET CURRENT DISTRIBUTION, V S = 15V
FIGURE 22. INPUT OFFSET CURRENT DISTRIBUTION, VS = 5V
14.2 14.1 14.0 13.9 VOUT (V) RL = 100k VOUT (V) 13.8 13.7 13.6 13.5 13.4 13.3 13.2 -40 -20 0 20 40 60 80 100 120 RL = 2k 50 UNITS MEDIAN
-13.1 -13.2 -13.3 -13.4 -13.5 -13.6 -13.7 -13.8 -13.9 -14.0 -14.1 -14.2 -40 -20 0 20 40 60 80 100 120 RL = 2k 50 UNITS MEDIAN
RL = 100k
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 23. VOH vs TEMPERATURE, VS = 15V
FIGURE 24. VOL vs TEMPERATURE, VS = 15V
200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.1m1m 10m100m 1
PHASE
GAIN
10 100 1k 10k100k1M 10M100M
200 180 160 140 120 100 80 60 40 20 0 -20 RL = 10k -40 CL = 100pF -60 SIMULATION -80 -100 0.1m1m 10m100m 1
OPEN LOOP GAIN (dB)/PHASE ()
OPEN LOOP GAIN (dB)/PHASE()
PHASE
GAIN
10 100 1k 10k100k1M 10M100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10k, CL = 10pF
FIGURE 26. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10k, CL = 100pF
11
FN6633.6 December 16, 2010
ISL28127, ISL28227 Typical Performance Curves VS = 15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
70 NORMALIZED GAIN (dB) 60 50 GAIN (dB) 40 30 20 10 0 AV = 10 Rg = 10k, Rf = 100k AV = 1 Rg = OPEN, Rf = 0 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) AV = 100 AV = 1000 Rg = 100, Rf = 100k Rg = 1k, Rf = 100k VS = 15V CL = 3.5pF RL = INF VOUT = 100mVP-P 15 13 11 9 7 5 3 1 -1 -3 -5 VS = 15V RL = 10k CL = 3.5pF AV = +2 VOUT = 100mVP-P 1k 10k 100k 1M 10M 100M Rf = Rg = 100 Rf = Rg = 1k Rf = Rg = 100k Rf = Rg = 10k
-10 100
FREQUENCY (Hz)
FIGURE 27. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 28. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE Rf/Rg
2 RL = 10k NORMALIZED GAIN (dB) RL = 1k NORMALIZED GAIN (dB) 1 0 -1 -2 -3 -4 VS = 15V CL = 3.5pF AV = +1 VOUT = 100mVP-P 10k 100k 1M 10M 100M RL = 499 RL = 100 RL = 49.9
7 6 5 4 3 2 1 0 -1 -2 -3 1k 10k 100k CL = 3.5pF 1M 10M 100M VS = 15V RL = 10k AV = +1 CL = 1000pF VOUT = 100mVP-P CL = 220pF CL = 100pF CL = 25.5pF
-5 1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 29. GAIN vs FREQUENCY vs RL
FIGURE 30. GAIN vs FREQUENCY vs CL
1 NORMALIZED GAIN (dB)
VS = 2.25V
6 5 4 LARGE SIGNAL (V) 3 2 1 0 1 -2 -3 -4 -5 RL = 2k RL = 10k VS = 15V CL = 3.5pF AV = 1 Rf = 0 Rg = inf VOUT = 10VP-P
0
-1 CL = 3.5pF RL = 10k AV = +1 VOUT = 100mVP-P 1k 10k
VS = 5V VS = 15V
-2
-3
100k
1M
10M
100M
-6
0
5
10
15 TIME (s)
20
25
30
FREQUENCY (Hz)
FIGURE 31. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 32. LARGE SIGNAL 10V STEP RESPONSE, VS = 15V
12
FN6633.6 December 16, 2010
ISL28127, ISL28227 Typical Performance Curves VS = 15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
2.4 2.0 SMALL SIGNAL (mV) 1.6 LARGE SIGNAL (V) 1.2 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 0 5 10 VS = 5V, RL = 2k, 10k CL = 3.5pF AV = 1 VOUT = 4VP-P 15 20 TIME (s) 25 30 35 40 VS = 15V, RL = 2k, 10k 80 60 40 20 0 20 40 60 80 0 0.2 0.4 0.6 RL = 2k CL = 3.5pF AV = 1 VOUT = 100mVP-P 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VS = 5V, 15V
TIME (ms)
FIGURE 33. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = 5V, 15V
FIGURE 34. SMALL SIGNAL TRANSIENT RESPONSE, VS = 5V, 15V
0.06 0.02 -0.02 INPUT (V) -0.06 -0.10 -0.14 -0.18 -0.20 -0.26 0 5 10 VS = 15V RL = 10k CL = 3.5pF AV = 100 Rf = 100k, Rg = 1k VIN = 200mVP-P INPUT
15 13 11 OUTPUT (V) 9 7 5 3 1 30 35 -1 40 INPUT (V)
0.26 0.22 0.08 0.04 0.10 0.06 0.02 -0.02 -0.06 0 5 10 15 20 25 TIME (s) 30 35 OUTPUT VS = 15V RL = 10k CL = 3.5pF AV = 100 Rf = 100k, Rg = 1k VIN = 200mVP-P INPUT
2 0 -2 -4 -6 -8 -10 -12 -14 40 OUTPUT (V)
OUTPUT 15 20 25 TIME (s)
FIGURE 35. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = 15V
FIGURE 36. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = 15V
90 80 OVERSHOOT (%) 70 60 50 40 30 20 10 0 10 100 1000 CAPACITANCE (pF) 10000 VS = 15V RL = 10k AV = 1 VOUT = 100mVP-P
E OV
T+ OO SH R -
OT HO RS VE O
FIGURE 37. % OVERSHOOT vs LOAD CAPACITANCE, VS = 15V
13
FN6633.6 December 16, 2010
ISL28127, ISL28227 Applications Information
Functional Description
The ISL28127 and ISL28227 are single and dual, low noise 10MHz BW precision op amps. Both devices are fabricated in a new precision 40V complementary bipolar DI process. A superbeta NPN input stage with input bias current cancellation provides low input bias current (1nA typical), low input offset voltage (10V typ), low input noise voltage (3nV/Hz), and low 1/f noise corner frequency (5Hz). These amplifiers also feature high open loop gain (1500V/mV) for excellent CMRR (120dB) and THD+N performance (0.0002% @ 3.5VRMS, 1kHz into 2k). A complimentary bipolar output stage enables high capacitive load drive without external compensation.
VINVIN+ RINRIN+ + V+ VOUT RL
V-
FIGURE 39. INPUT ESD DIODE CURRENT LIMITING DIFFERENTIAL INPUT
Output Current Limiting
The output current is internally limited to approximately 45mA at +25C and can withstand an short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long term reliability.
Operating Voltage Range
The devices are designed to operate over the 4.5V (2.25V) to 40V (20V) range and are fully characterized at 10V (5V) and 30V (15V). Parameter variation with operating voltage is shown in the "Typical Performance Curves" beginning on page 8.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, and an additional anti-parallel diode pair across the inputs (see Figures 38 and 39).
V+ VIN RIN +
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28127 and ISL28227 are immune to output phase reversal, even when the input voltage is 1V beyond the supplies.
VOUT RL
Power Dissipation
It is possible to exceed the +150C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1:
T JMAX = T MAX + JA xPD MAXTOTAL (EQ. 1)
V-
FIGURE 38. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
For unity gain applications (see Figure 38) where the output is connected directly to the non-inverting input a current limiting resistor (RIN) will be needed under the following conditions to protect the anti-parallel differential input protection diodes. * The amplifier input is supplied from a low impedance source. * The input voltage rate-of-rise (dV/dt) exceeds the maximum slew rate of the amplifier (3.6V/s). If the output lags far enough behind the input, the anti-parallel input diodes can conduct. For example, if an input pulse ramps from 0V to +10V in 1s, then the output of the ISL28x27 will reach only +3.6V (slew rate = 3.6V/s) while the input is at 10V, The input differential voltage of 6.4V will force input ESD diodes to conduct, dumping the input current directly into the output stage and the load. The resulting current flow can cause permanent damage to the ESD diodes. The ESD diodes are rated to 20mA, and in the previous example, setting RIN to 1k resistor (see Figure 38) would limit the current to < 6.4mA, and provide additional protection up to 20V at the input. In applications where one or both amplifier input terminals are at risk of exposure to high voltage, current limiting resistors may be needed at each input terminal (see Figure 39 RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA. 14
where: * PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) * PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX PD MAX = V S x I qMAX + ( V S - V OUTMAX ) x -----------------------R
L
(EQ. 2)
where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of 1 amplifier * VS = Total supply voltage * IqMAX = Maximum quiescent supply current of 1 amplifier * VOUTMAX = Maximum output voltage swing of the application RL = Load resistance
FN6633.6 December 16, 2010
ISL28127, ISL28227
ISL28127 and ISL28227 SPICE Model
Figure 40 shows the SPICE model schematic and Figure 41 shows the net list for the ISL28127 and ISL28227 SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC parameters are VOS, IOS, total supply current and output voltage swing. The model does not model input bias current. The model uses typical parameters given in the "Electrical Specifications" Table beginning on page 4. The AVOL is adjusted for 128dB with the dominate pole at 5Hz. The CMRR is set higher than the "Electrical Specifications" Table to better match design simulations (150dB, f = 50Hz). The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25C. Figures 42 through 57 show the characterization vs simulation results for the Noise Voltage, Closed Loop Gain vs Frequency, Closed Loop Gain vs Rf/Rg, Closed Loop Gain vs RL, Closed Loop Gain vs CL, Large Signal 10V Step Response, Open Loop Gain Phase and Simulated CMRR vs Frequency.
LICENSE STATEMENT
The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as "Licensee", a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macromodel, in whole, in part, or in modified form, to anyone outside the Licensee's company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided "AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE." In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice.
15
FN6633.6 December 16, 2010
ISL28127, ISL28227
.
V++ R3 4.45k 4 CASCODE Q4 C4 2.5pF SUPERB R1 5E11 0.1V 25 R17 377.4 En In+ C6 2pF IOS VCM 1E-9 R2 5E11 IEE 200E-6 9 + VOS 10E-6 1 Mirror Q3 + 7 EOS 2 5 Q5 3 SUPERB Q1 Q2 8 DX C5 2.5pF R4 4.45k CASCODE 6 D1 IEE1 96E-6
V++ 4 5
VIN-
VinV5 24 D12 DN +
+ -
Vc Vmid
+ + -
VIN+
V-VCM
Voltage Noise
V++ G1 4 D2 DX + V1 - 1.86V 11 G3 R5 1 D4 DX + V3 - 1.86V Vg
Input Stage
V++ G5 R7 572.9E6 C2 55.55pF R9 1 L1 3.18E-3 17 R11 1 Vc Vg R12 1 18 L2 3.18E-3 V--
+ -
10
+ -
13
+ -
5 Vc
Vmid
Vmid
G2 + 12 V2 1.86V
R6 1
G4 + 14 V4 1.86V
R8 572.9E6
C3 55.55pF
R10 1
G6
V-VCM
D3 DX
D5 DX
VCM
1ST Gain Stage
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
V++ D8 DX 22 ISY 2.2mA D6 DX 20 23 D9 DX V5 + G7
V+
+ -
V+ + E2
Vg
1.12V D7 DX V6 21 1.12V G8 + -
V-
+ V--
+
E3
V-
D10 DY
+ G9
+ G10
D11 DY
Supply Isolation Stage
FIGURE 40. SPICE SCHEMATIC
Output Stage
16
+ -
+ +
VOUT
+ -
+ -
R15 90 VOUT
R16 90
FN6633.6 December 16, 2010
ISL28127, ISL28227
* source ISL28127_SPICEmodel * Revision C, August 8th 2009 LaFontaine * Model for Noise, supply currents, 150dB f=50Hz CMRR, *128dB f=5Hz AOL *Copyright 2009 by Intersil Corporation *Refer to data sheet "LICENSE STATEMENT" Use of *this model indicates your acceptance with the *terms and provisions in the License Statement. * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28127subckt Vin+ Vin-V+ V- VOUT * source ISL28127_SPICEMODEL_0_0 * *Voltage Noise E_En IN+ VIN+ 25 0 1 R_R17 25 0 377.4 TC=0,0 D_D12 24 25 DN V_V7 24 0 0.1 * *Input Stage I_IOS IN+ VIN- DC 1e-9 C_C6 IN+ VIN- 2E-12 R_R1 VCM VIN- 5e11 TC=0,0 R_R2 IN+ VCM 5e11 TC=0,0 Q_Q1 2 VIN- 1 SuperB Q_Q2 3 8 1 SuperB Q_Q3 V-- 1 7 Mirror Q_Q4 4 6 2 Cascode Q_Q5 5 6 3 Cascode R_R3 4 V++ 4.45e3 TC=0,0 R_R4 5 V++ 4.45e3 TC=0,0 C_C4 VIN- 0 2.5e-12 C_C5 8 0 2.5e-12 D_D1 6 7 DX I_IEE 1 V-- DC 200e-6 I_IEE1 V++ 6 DC 96e-6 V_VOS 9 IN+ 10e-6 E_EOS 8 9 VC VMID 1 * *1st Gain Stage G_G1 V++ 11 4 5 0.0487707 G_G2 V-- 11 4 5 0.0487707 R_R5 11 V++ 1 TC=0,0 R_R6 V-- 11 1 TC=0,0 D_D2 10 V++ DX D_D3 V-- 12 DX V_V1 10 11 1.86 V_V2 11 12 1.86 * *2nd Gain Stage G_G3 V++ VG 11 VMID 4.60767E-3 G_G4 V-- VG 11 VMID 4.60767E-3 R_R7 VG V++ 572.958E6 TC=0,0 R_R8 V-- VG 572.958E6 TC=0,0 C_C2 VG V++ 55.55e-12 TC=0,0 C_C3 V-- VG 55.55e-12 TC=0,0 D_D4 13 V++ DX D_D5 V-- 14 DX V_V3 13 VG 1.86 V_V4 VG 14 1.86 * *Mid supply Ref R_R9 VMID V++ 1 TC=0,0 R_R10 V-- VMID 1 TC=0,0 I_ISY V+ V- DC 2.2E-3 E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 * *Common Mode Gain Stage with Zero G_G5 V++ VC VCM VMID 31.6228e-9 G_G6 V-- VC VCM VMID 31.6228e-9 R_R11 VC 17 1 TC=0,0 R_R12 18 VC 1 TC=0,0 L_L1 17 V++ 3.183e-3 L_L2 18 V-- 3.183e-3 * *Output Stage with Correction Current Sources G_G7 VOUT V++ V++ VG 1.11e-2 G_G8 V-- VOUT VG V-- 1.11e-2 G_G9 22 V-- VOUT VG 1.11e-2 G_G10 23 V-- VG VOUT 1.11e-2 D_D6 VG 20 DX D_D7 21 VG DX D_D8 V++ 22 DX D_D9 V++ 23 DX D_D10 V-- 22 DY D_D11 V-- 23 DY V_V5 20 VOUT 1.12 V_V6 VOUT 21 1.12 R_R15 VOUT V++ 9E1 TC=0,0 R_R16 V-- VOUT 9E1 TC=0,0 * .model SuperB npn + is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50 + re=0.065 rc=35 cje=1.5E-12 cjc=2E-12 + kf=0 af=0 .model Cascode npn + is=502E-18 bf=150 va=300 ik=17E-3 rb=140 + re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f + kf=0 af=0 .model Mirror pnp + is=4E-15 bf=150 va=50 ik=138E-3 rb=185 + re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12 + kf=0 af=0 .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28127subckt
FIGURE 41. SPICE NET LIST
17
FN6633.6 December 16, 2010
ISL28127, ISL28227 Characterization vs Simulation Results
100 INPUT NOISE VOLTAGE (nV/Hz) VS = 19V AV = 1 INPUT NOISE VOLTAGE (nV/Hz) 100
10
10
V(INOISE) 1 0.1
1 0.1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 42. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 43. SIMULATED INPUT NOISE VOLTAGE
70 60 50 GAIN (dB) 40 30 20 10 0 AV = 10 Rg = 10k, Rf = 100k AV = 1 Rg = OPEN, Rf = 0 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M AV = 100 AV = 1000 Rg = 100, Rf = 100k Rg = 1k, Rf = 100k GAIN (dB) VS = 15V CL = 3.5pF RL = INF VOUT = 100mVP-P
70 60 50 40 30 20 10 0 AV = 10 Rg = 10k, Rf = 100k AV = 1 Rg = OPEN, Rf = 0 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M AV = 100 AV = 1000 Rg = 100, Rf = 100k Rg = 1k, Rf = 100k
-10 100
-10 100
FIGURE 44. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 45. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
15 NORMALIZED GAIN (dB) 13 11 9 7 5
Rf = Rg = 100k NORMALIZED GAIN (dB) Rf = Rg = 10k
15 13 11 9 7 5 3 VS = 15V RL = 10k 1 CL = 3.5pF -1 A = +2 V -3 VOUT = 100mVP-P -5 1k 10k
Rf = Rg = 100k
Rf = Rg = 10k Rf = Rg = 1k Rf = Rg = 100
Rf = Rg = 1k
3 VS = 15V RL = 10k 1 CL = 3.5pF -1 A = +2 V -3 VOUT = 100mVP-P -5 1k 10k
Rf = Rg = 100
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 46. CHARACTERIZED CLOSED LOOP GAIN vs R f/Rg
FIGURE 47. SIMULATED CLOSED LOOP GAIN vs Rf/Rg
18
FN6633.6 December 16, 2010
ISL28127, ISL28227 Characterization vs Simulation Results (Continued)
2 RL = 10k NORMALIZED GAIN (dB) 1 0 -1 -2 VS = 15V -3 -4 -5 1k CL = 3.5pF AV = +1 VOUT = 100mVP-P 10k RL = 49.9 RL = 499 RL = 100 NORMALIZED GAIN (dB) RL = 1k 1 RL = 10k 0 RL = 1k -1 -2 VS = 15V -3 -4 100k 1M FREQUENCY (Hz) 10M 100M -5 1k CL = 3.5pF AV = +1 VOUT = 100mVP-P 10k RL = 499 RL = 100 2
RL = 49.9 100k 1M FREQUENCY (Hz) 10M 100M
FIGURE 48. CHARACTERIZED CLOSED LOOP GAIN vs R L
FIGURE 49. SIMULATED CLOSED LOOP GAIN vs RL
7 6 NORMALIZED GAIN (dB) 5 4 3 2 1 0 -1 -2 -3 1k 10k CL = 3.5pF 100k 1M FREQUENCY (Hz) 10M 100M VS = 15V RL = 10k AV = +1 VOUT = 100mVP-P
7 6 NORMALIZED GAIN (dB) CL = 1000pF CL = 220pF CL = 100pF CL = 25.5pF 5 4 3 2 1 0 -1 -2 -3 1k 10k CL = 25.5pF CL = 3.5pF 100k 1M FREQUENCY (Hz) 10M 100M CL = 220pF CL = 100pF VS = 15V RL = 10k AV = +1 VOUT = 100mVP-P CL = 1000pF
FIGURE 50. CHARACTERIZED CLOSED LOOP GAIN vs C L
FIGURE 51. SIMULATED CLOSED LOOP GAIN vs CL
6 5 4 LARGE SIGNAL (V) 3 2 1 0 1 -2 -3 -4 -5 -6 0 5 10 15 TIME (s) 20 25 30 RL = 2k RL = 10k LARGE SIGNAL (V) VS = 15V CL = 3.5pF AV = 1 Rf = 0, Rg = INF VOUT = 10VP-P
6 5 4 3 2 1 0 1 -2 -3 -4 -5 -6 0 5 10 15 TIME (s) 20 25 30 RL = 10k VS = 15V CL = 3.5pF AV = 1 Rf = 0, Rg = INF VOUT = 10VP-P
FIGURE 52. CHARACTERIZED LARGE SIGNAL 10V STEP RESPONSE
FIGURE 53. SIMULATED LARGE SIGNAL 10V STEP RESPONSE
19
FN6633.6 December 16, 2010
ISL28127, ISL28227 Characterization vs Simulation Results (Continued)
200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.1m 1m 10m100m 1 200 OPEN LOOP GAIN (dB)/PHASE () 150 PHASE 100 50 0 GAIN OPEN LOOP GAIN (dB)/PHASE () PHASE
GAIN
10 100 1k 10k 100k 1M 10M100M FREQUENCY (Hz)
RL = 10k -50 CL = 10pF MODEL VOS SET TO ZERO FOR THIS TEST -100 0.1Hz 10Hz 1.0k
100k
10M
FREQUENCY (Hz)
FIGURE 54. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
FIGURE 55. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
130 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 10
150 VS = 5V VS = 2.25V 100 CMRR (dB)
CMRR (dB)
VS = 15V
50
RL = INF CL = 5.25pF AV = +1 VCM = 1VP-P 100 1k 10k 100k 1M 10M
0
GENERATED USING FULL MODEL. CMRR DELTA INPUT BASE VOLTAGE/VCM INPUT VOLTAGE 1.0Hz 100Hz 10k 1.0M 100M 10G 1.0T
-50 10m
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 56. CHARACTERIZED CMRR vs FREQUENCY
FIGURE 57. SIMULATED CMRR vs FREQUENCY
20
FN6633.6 December 16, 2010
ISL28127, ISL28227 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
REVISION FN6633.6 DATE CHANGE 12/13/10 page 3: The ISL28227 8 LD TDFN Pin configuration: Vout_A and Vout_B labels on pins 1 and 7 changed to VoutA and VoutB Figure 8: labeled red curve Vs = 5V and blue curve Vs = 15V. 12/10/10 -Converted to New Intersil Template -Added AN1509 in Related Literature on page 1 -Removed Titles from Graphics on page 1 and replaced with Figure names -Changed copyright to legal's suggested verbiage on page 1 -Updated Ordering Information table on page 2. Removed Coming Soon for ISL28127FRTBZ and ISL28127FUBZ parts. Added in the Vos (MAX) numbers in those rows (75 and 70 respectively). -Changed Tape and Reel Note in ordering information to "Add T*..." to include all Tape and Reel additions -Updated Electrical Spec Table page 4 and page 5 for Vos and TCVos oAdded data row for Offset Voltage; MSOP Grade B Package; ISL28127 oAdded data row for Offset Voltage; TDFN Grade B Package; ISL28127 oAdded data row for Offset Voltage Drift; MSOP Grade B Package; ISL28127 oAdded data row for Offset Voltage Drift; TDFN Grade B Package; ISL28127 oRemoved - Temperature data established by characterization from conditions (New standard note covers this verbiage) oChanged Note: "Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested". TO: Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. -Updated Typical Performance Curves oUpdated typical plot of Vos vs Temp for Figure 8. oAdded: IB+ vs Temp vs Vsupply plot; IB- vs Temp vs Vsupply plot; Ios vs Temp vs Vsupply plot; Figures 9, 10, 11 oAdded: Vos distribution Vs=15V plot; Vos distribution Vs=5V plot; TCVos distribution Vs=15V plot; TCVos distribution Vs=5V plot; TCIB+ distribution Vs=15V plot; TCIB+ distribution Vs=5V plot; TCIB- distribution Vs=15V plot; TCIB- distribution Vs=5V plot; TCIos distribution Vs=15V plot; TCIos distribution Vs=5V plot (Figures 13 thru 22) FN6633.5 9/10/10 - Updated ordering information by removing Note 2, which referenced "-T13" tape and reel option and revised Note 1 to include "-T7A" tape and reel option. Removed Note reference next to part numbers and placed under part number in table head indicating that it references all parts. Change shows that all parts now have -T7, -T7A, and -T13 tape and reel options. 7/2/10 In "Ordering Information" on page 2: Removed "Coming Soon" from ISL28127FRTZ, ISL28227FRTBZ, ISL28227FRTZ, ISL28227FUBZ & ISL28227FUZ. Updated the part marking for ISL28127FRTBZ from "127Z" to "8127" Updated the part marking for ISL28127FRTZ from "-C 127Z" to "-C 8127" Updated the part marking for ISL28227FRTBZ from "227Z" to "8227" Updated the part marking for ISL28227FRTZ from "-C 227Z" to "-C 8227" Added VOS of 75V for ISL28227FRTBZ Added VOS of 75V for ISL28227FUBZ Added Evaluation Boards ISL28127MSOPEVAL1Z and ISL28227SOICEVAL2Z In "Thermal Information" on page 4, for 8 Ld TDFN, corrected Theta JA note from Note 5 to Note 4. In VS 15V "Electrical Specifications" table on page 4, added VOS specs for ISL28227 MSOP, TDFN Grade B Packages. Added TCVOS specs for ISL28227 MSOP, TDFN Grade B Packages Changed TYP for "Offset Voltage; MSOP, TDFN Grade C Package" from 10V to -10V In VS 5V "Electrical Specifications" table on page 6, added VOS specs for SOIC ISL28227. Added VOS specs for MSOP, TDFN Grade B and C Packages. Added TCVOS specs for SOIC ISL28227. Added TCVOS specs for MSOP, TDFN Grade B and C Packages FN6633.3 3/11/10 PODs M8.118 and L8.3x3A - Updated to new intersil format by adding land pattern and moving dimensions from table onto drawing. 3/3/10 On page 2: Under "Ordering Information" ISL28227FBZ: Changed Vos max from 80V to 75V On page 4: Changed: 1. ISL28227 SOIC Room Temp limit for Vos from 80V (MAX) and -80V (MIN) to 75V (MAX) and -75V (MIN). 2. ISL28227 SOIC Full Temp limit for Vos from 160V (MAX) and -160V (MIN) to 150V (MAX) and -150V (MIN) 3. ISL28227 SOIC limit for TCVos from 0.8V (MAX) and -0.8V (MIN) to 0.75V (MAX) and -0.75V (MIN)
FN6633.4
21
FN6633.6 December 16, 2010
ISL28127, ISL28227 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued)
REVISION FN6633.3 (Continued) DATE 3/2/10 CHANGE In "Absolute Maximum Ratings" on page 4, HBM for ISL28227 changed from "4kV" to "6kV" In "Thermal Information" on page 4, Tjc values for ISL28227 changed: For MSOP from "50" to "45" For SOIC from "60" to "55" Vos (Max) (uV) TBD instead of 70 TBD instead of 70 150 instead of 70 80 instead of 70 TBD instead of 70 150 instead of 70
2/25/10 In the "Ordering Information" (page 2): Part Number Part Marking ISL28127FRTBZ ISL28127FRTZ -C 127Z instead of 127Z C ISL28127FUBZ ISL28127FUZ 8127Z -C instead of 8127Z Removed "Coming Soon) for ISL28127FUZ package ISL28227FBZ Removed "Coming Soon) for ISL28227FBZ package ISL28227FRTBZ ISL28227FRTZ -C 227Z instead of 227Z C ISL28227FUZ 8227Z -C instead of 8227Z Added the following row of data ISL28227FUBZ 8227Z
TBD
In the "Electrical specifications" on page 4 and page 6 the following changes were made. The change applies to the same spec found on page 4 and page 6. VOS Offset Voltage; SOIC Package, ISL28127: Added -70 to MIN across room temp and -120 MIN across full temp VOS Offset Voltage; SOIC Package, ISL28227: Added -80 to MIN across room temp and -160 MIN across full temp VOS Offset Voltage; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -150 to MIN across room temp and 250 MIN across full temp TCVOS Offset Voltage Drift; SOIC Package, ISL28127: Added -0.5 to MIN across full temp TCVOS Offset Voltage Drift; SOIC Package, ISL28227: Added -0.8 to MIN across full temp TCVOS Offset Voltage Drift; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -1 to MIN across full temp IOS Input Offset Current: Added -10 to MIN across room temp and -12 to MIN across full temp IB Input Bias Current:Added -10 to MIN across room temp and -12 to MIN across full temp 2/19/10 In the "Ordering Information" (page 2), added differentiated part numbers for B-grade and C-grade for TDFN and MSOP. In "Absolute Maximum Ratings" on page 4, added ESD and latch-up information. In "Thermal Information" on page 4, broke out Theta JA to list the single and dual and added Theta JC. FN6633.2 1/29/10 Added license statement for P-Spice Model. Updated Spice Schematic by adding capacitors C4, C5 and C6 Updated Spice Net List as follows: From: Revision B, July 23 2009 To: Revision C, August 8th 2009 LaFontaine From: source ISL28127_SPICEMODEL_7_9 To: source ISL28127_SPICEMODEL_0_0 Added after I_IOS: C_C6 IN+ VIN- 2E-12 Added after R_R4: C_C4 VIN- 0 2.5e-12 C_C5 8 0 2.5e-12 From: .ends ISL28127 To: .ends ISL28127subckt Replaced POD MDP0027 with M8.15E to match ASYD in Intrepid (no dimension changes; the PODs are the same. The change was to update to the Intersil format, moving dimensions from table onto drawing and adding land pattern)
22
FN6633.6 December 16, 2010
ISL28127, ISL28227 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued)
REVISION FN6633.1 DATE CHANGE 9/14/09 "Functional Description" on page 14. Corrected low 1/f noise corner frequency from 3Hz to 5Hz to match Figure 2 on page 1. Corrected high open loop gain from 1400V/mV to 1500V/mV to match "Open-Loop Gain" on page 5 spec table. "Operating Voltage Range" on page 14. Removed following 2 sentences since there are no graphs illustrating common mode voltage sensitivity vs temperature or VOS as a function of supply voltage and temperature: "The input common mode voltage sensitivity to temperature is shown in Figure 3 (15V). Figure 20 shows VOS as a function of supply voltage and temperature with the common mode voltage at 0V for split supply operation." 9/2/09 Added Theta JC in "Thermal Information" on page 4 for TDFN package 7/21/09 Updated Features to show only key features and updated applications section. Added Typical Application Circuit and performance graph, Updated Ordering Information to match Intrepid and added POD's L8.3x3A and M8.118, also added MSL level as part of new format. Added TDFN pinouts, updated pin descriptions to include TDFN pinouts, Added Theta Ja in Thermal information for TDFN and MSOP packages. Added Revision History and Products Text with device info links. Added SPICE Model with referencing text and Net List. FN6633.0 5/28/09 Techdocs Issued File Number FN6633. Initial release of Datasheet with file number FN6633 making this a Rev 0.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28127, ISL28227 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
23
FN6633.6 December 16, 2010
ISL28127, ISL28227
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09
4 4.90 0.10 A DETAIL "A" 0.22 0.03
B
6.0 0.20 3.90 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45 1.27 0.43 0.076 0.25 M C A B 4 4
SIDE VIEW "B" TOP VIEW
1.75 MAX
1.45 0.1 0.25 0.175 0.075 GAUGE PLANE C SEATING PLANE 0.10 C
SIDE VIEW "A
0.63 0.23
DETAIL "A"
(1.27) (0.60)
NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012.
2. (5.40) 3. 4.
TYPICAL RECOMMENDED LAND PATTERN
24
FN6633.6 December 16, 2010
ISL28127, ISL28227
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10
( 2.30) 3.00 A B ( 1.95)
( 8X 0.50) 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PIN 1 (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN (1.50) ( 2.90 )
SEE DETAIL "X" 2X 1.950 6X 0.65 PIN #1 INDEX AREA 6 1.50 0.10 1 SIDE VIEW 0.75 0.05 0.10 C C 0.08 C
8 8X 0.30 0.10 2.30 0.10 BOTTOM VIEW 8X 0.30 0.05 0.10 M C A B 4
C
0 . 2 REF
5
0 . 02 NOM. 0 . 05 MAX. DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
2. 3. 4.
25
FN6633.6 December 16, 2010
ISL28127, ISL28227
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10
5 3.00.05 A 8 D DETAIL "X"
1.10 MAX
SIDE VIEW 2 4.90.15
0.09 - 0.20
3.00.05 5
PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW
0.95 REF
GAUGE PLANE
0.25
0.55 0.15 H 0.85010 DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D SIDE VIEW 1 0.10 0.05 0.10 C
33
(5.80) (4.40) (3.00) NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only.
(0.65) (0.40) (1.40)
TYPICAL RECOMMENDED LAND PATTERN
26
FN6633.6 December 16, 2010

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